1. Field of the Invention
Embodiments of the invention relates to semiconductor memory devices. In particular, embodiments of the invention relate to flash memory devices and a method of programming flash memory devices.
2. Discussion of Related Art
The development of an ever-widening range of mobile electronic devices and related applications has generated an increasing demand for flash memories and systems adapted to the control and programming of flash memories. Flash memories are particularly well suited to mobile device applications because they are capable of storing a large amount of data in a non-volatile manner. Flash memory is, however, not without its own shortcomings—most notably longer read and write cycles, as compared with random access memories.
However, this particular drawback can be overcome to a certain extent by the use of buffer memories. For example, data from a host device may be first stored in a buffer memory instead of being directly in the flash memory. Thereafter, data initially stored in the buffer memory may be transferred to the flash memory in similar vein, data being read from the flash memory may be first stored in the buffer memory before being transferred to the host device. This buffered mode of data transfer improves the performance of flash memory within memory systems supporting various host devices and related applications.
Conventional flash memory comes in two types; NAND type and NOR type. A NAND flash memory includes a memory cell array adapted to store data. This memory cell array consists of a plurality of cell strings, each referred to as a “NAND string.” A page buffer is provided within the NAND flash memory to store data being programmed to the memory cell array or read from the memory cell array. As well known in the art, the memory cells forming a NAND flash memory may be erased and/or programmed using a phenomenon called Fowler-Nordheim tunneling current. Exemplary methods adapted to erase and program a NAND flash memory are disclosed, for example, in U.S. Pat. Nos. 5,473,563 and 5,696,717, the subject matter of which is hereby incorporated by reference.
A flowchart describing a program operation for a conventional flash memory device is illustrated in Figure (FIG.) 1. Referring to FIG. 1, as a program operation commences, the data to be programmed is loaded into a page buffer (S10). After the data to be programmed is loaded into the page buffer, a high voltage generating circuit is activated to generate various voltage signals, such as word line voltages, including a program voltage, a pass voltage, and the like (S20). Once word line voltages reach their target voltages, a program operation is executed. As is conventionally understood, the data loaded in the page buffer is stored in memory cells using iterative program loops. Each of the program loops includes programming memory cells with the loaded data (S30), reading the resulting program states (i.e., verifying the program states) of memory cells (S40), and determining whether the memory cells are programmed to a target (i.e., normal) threshold voltage (S50). The program loop (S30-S50) is run iteratively for a given number of cycles until a defined set of memory cells are all programmed to the target threshold voltage.
The total time required for this program operation is defined by the sum of “data transfer time”, (i.e., the time required to transfer data to a page buffer), “high voltage enable time”, (i.e., the time required to generate the high voltage signals), and the “program loop time” (i.e., the time required to iteratively run through the program loops). Practically speaking, it is difficult to reduce the data transfer time and the high voltage enable time that occupy most of the total program time. Yet contemporary host devices demand further reductions in the total program time.